When must the op amp be active?

In the era of the Internet of Things, battery-powered applications are on the rise. This article explores how you can achieve significant power savings without compromising performance—specifically, by using an amplifier’s disable pin effectively. Many operational amplifiers come with a disable pin that, when used correctly, can reduce power consumption by up to 99% while maintaining accuracy. The disable pin is typically used in standby mode, where the entire IC enters a low-power state. This means the device doesn’t need to process signals continuously, resulting in a dramatic drop in power usage. For example, if the op amp is used as a buffer for an ADC (as shown in Figure 1), it must be active during signal processing. However, if the disable pin is activated, the amplifier can still maintain low power consumption as long as the ADC isn’t sampling new data. This approach works well when the ADC is not actively taking measurements. Figure 1: Typical schematic of an ADC input stage with an ADC driver and a reference buffer. The key question is: When should the op amp be active? It needs to operate before the conversion starts, enough time for the internal input capacitor to charge to the correct voltage. The required time depends on factors like the capacitor size, voltage level, and the op amp’s ability to drive capacitive loads. According to the AD7980 ADC datasheet, the input capacitance is 30pF when connected with 400Ω impedance. However, op amps have different characteristics. For instance, the ADA4807 has a listed capacitive load of 15pF but can handle more, as seen in Figure 2. Figure 2: Frequency response of the ADA4807. This graph shows that the amplifier can drive high capacitive loads effectively. When disabled, it takes about 500ns to reach full-scale output (5V or 4.096V). To be safe, we assume the amplifier is turned on 750ns before the conversion begins. When comparing 1kSPS and 1MSPS, the power savings are impressive. At 1kSPS, power consumption drops to 0.02mW, saving 99.83%. At 1MSPS, the total power is 10.75mW, representing a 92.41% reduction. These savings apply not only to the ADC driver but also to the reference buffer. This example highlights the capabilities of modern devices. With a minimum sampling time of 500ns, the SINAD deviation remains below 0.5dB. When choosing drivers, focus on faster devices and use them wisely. We’ve considered a simple buffer configuration (gain = 1), but for inverting or other configurations, power savings may vary and require further testing.

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