The Xilinx UltraScaleTM architecture delivers unprecedented ASIC-level system-level integration and capacity for the most demanding applications.
The UltraScale architecture is the industry's first application of the most advanced ASIC architecture optimization in the All Programmable architecture. The architecture can scale from a 20nm planar FET structure to a 16nm fin FET transistor technology and even higher technology, while extending from a single chip to a 3D IC. With the analytical collaborative optimization of the Xilinx Vivado® design suite, the UltraScale architecture provides massive data routing while intelligently addressing the number one system performance bottleneck on advanced process nodes. This collaborative design achieves over 90% utilization without compromising performance.
Breakthroughs in the UltraScale architecture include :
• Strategically ASIC-like system clocks can be strategically placed anywhere on the chip, reducing clock skew by up to 50%
• There are a large number of parallel buses in the system architecture, eliminating the need for pipelines that cause delays, which increases system speed and capacity
• Eliminate potential timing closure issues and interconnect bottlenecks even in systems that require resource utilization of 90% or more
• Build larger devices with 3D IC integration capabilities and lead a full generation of current industry standards in process technology
• Significantly improve system performance over lower system power budgets, including multi-Gb serial transceivers, I/O, and memory bandwidth
• Significantly enhance DSP and packet processing performance
The Xilinx UltraScale architecture opens up a whole new dimension for designers of very large capacity solutions.
The more the better
Since the introduction of the concept of "all things digital", "the more the better" has become a basic and inevitable development trend of digital systems in all market sectors. This expectation has become the basic driving force for systems to demand higher resolution, higher bandwidth and greater storage. The concept of "more" also logically triggers the following facts:
• More devices generate more data.
• More data means that data must flow faster.
• More fast-moving data requires faster calculations.
• More applications require faster access to more data.
• Increased data volumes and increased data rates place higher demands on data integrity.
Data creation and data transfer rates are increasing rapidly in almost every area, which will increase the demand for new device architectures to address the challenges of the following issues:
• Massive data streams and clocking similar to ASICs
• Massive I/O and memory bandwidth
• Faster DSP and packet processing
• Power management
• Multi-level security
UltraScale Architecture: Xilinx's Next-Generation All Programmable Architecture
In order to achieve system performance of hundreds of Gbs per second and intelligent processing at full line rate, and to extend to Tb level and teraflops per second, a new architectural approach is required. To do this, we need to do more than simply improve the performance of each transistor or system module, or expand the number of modules in the system, but fundamentally improve communication, clock, critical path and interconnection functions to meet Massive data streams, real-time packet and image processing requirements.
The UltraScaleTM architecture addresses these challenges by requiring massive I/O and memory bandwidth, massive data streams, and superior DSP and packet processing performance by applying state-of-the-art ASIC technology in a fully programmable (All Programmable) architecture. . The UltraScale architecture is fine-tuned to provide massive cabling capabilities and is collaboratively optimized with Vivado® design tools, so the architecture's utilization is at an unprecedentedly high level (over 90%) without compromising performance.
The UltraScale architecture is the industry's first to use the most advanced ASIC architecture in the All Programmable architecture to optimize the architecture from 20nm planar FET structures to 16nm fin FET transistor technology and even higher technology, while extending from a single chip to a 3D IC. The UltraScale architecture not only addresses the limitations of total system throughput expansion and latency, but also directly addresses the number one system performance bottleneck on advanced process nodes, namely interconnect issues.
The Xilinx UltraScale architecture is designed to meet next-generation system-level performance requirements. (see picture 1)
Xilinx has made hundreds of design enhancements to the UltraScale architecture and combined these improvements to enable design teams to build systems that are more powerful, faster, and more power-hungry than ever before. See Figure 2.
Figure 2: Xilinx UltraScale Architecture
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