According to Shang-Yi Chiang, senior vice president of research and development at Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC), at the Tech Forum held in the United States recently, the company will continue to use the FinFET technology to continue the semiconductor process miniaturization for the next ten years. The path is clearly visible and can reach the 7nm node; however, below the 7nm node, the biggest challenge in semiconductor process miniaturization comes from the economy, not the technology.
Jiang Shangyi stated that he is confident that the semiconductor industry will find solutions to overcome technical obstacles below 7nm in the next ten years. However, he also pointed out that although the new technology can achieve mass production of node chips below 7nm, it may have to pay a high price: " As process nodes evolved, we also saw a significant increase in wafer fabrication costs over previous generation processes."
In another keynote speech at the ARM Technology Forum, Chi-Ping Hsu, Senior Vice President of R&D for Silicon Realization Division of Cadence Design Systems, an EDA supplier, demonstrated the transition from 32/28nm to 22/ The 20nm node process technology R&D cost increases; he cited an example that if the 32/28nm node costs 1.2 billion U.S. dollars to reach the 22/20nm node, the cost scale will increase to 21 to 3 billion U.S. dollars.
As for the chip design cost, it will increase from the 50 to 90 million US dollars required for the 32-nm node to 22-50 million US dollars at the 22-nm node. Xu Jiping also pointed out that at the 32nm node, the chip sales volume needs to reach 30 to 40 million, in order to level the cost; but to the 20nm node, the threshold will increase to 60 million to 100 million.
FinFET is a 3D transistor technology that is currently gaining initial adoption from chip makers; the big maker Intel is calling its 3D transistor technology "tri-gate," and the industry expects the company to The bottom is to launch 22nm chip samples produced using 3D transistor technology.
Jiang Shangyi said that the 22nm node will be the last era of the planar transistor technology used by the semiconductor industry: "After this, the technology will be resigned."
Jiang Shangyi stated that he is confident that the semiconductor industry will find solutions to overcome technical obstacles below 7nm in the next ten years. However, he also pointed out that although the new technology can achieve mass production of node chips below 7nm, it may have to pay a high price: " As process nodes evolved, we also saw a significant increase in wafer fabrication costs over previous generation processes."
In another keynote speech at the ARM Technology Forum, Chi-Ping Hsu, Senior Vice President of R&D for Silicon Realization Division of Cadence Design Systems, an EDA supplier, demonstrated the transition from 32/28nm to 22/ The 20nm node process technology R&D cost increases; he cited an example that if the 32/28nm node costs 1.2 billion U.S. dollars to reach the 22/20nm node, the cost scale will increase to 21 to 3 billion U.S. dollars.
As for the chip design cost, it will increase from the 50 to 90 million US dollars required for the 32-nm node to 22-50 million US dollars at the 22-nm node. Xu Jiping also pointed out that at the 32nm node, the chip sales volume needs to reach 30 to 40 million, in order to level the cost; but to the 20nm node, the threshold will increase to 60 million to 100 million.
FinFET is a 3D transistor technology that is currently gaining initial adoption from chip makers; the big maker Intel is calling its 3D transistor technology "tri-gate," and the industry expects the company to The bottom is to launch 22nm chip samples produced using 3D transistor technology.
Jiang Shangyi said that the 22nm node will be the last era of the planar transistor technology used by the semiconductor industry: "After this, the technology will be resigned."
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