In high-speed HDI (High-Density Interconnect) PCB design, via design plays a critical role. A via consists of three main components: the hole itself, the annular pad around the hole, and the power layer isolation area. Vias are typically categorized into three types: blind vias, buried vias, and through-holes. Understanding the parasitic capacitance and inductance associated with vias is essential for optimizing high-speed PCB performance.
Today, high-speed PCBs are widely used in various fields such as telecommunications, computing, and image processing. These boards are designed to meet demands for low power consumption, minimal electromagnetic radiation, high reliability, compact size, and lightweight. To achieve these goals, careful via design becomes an essential part of the overall PCB layout.
**1. Through-Hole Vias**
Through-hole vias are one of the most common types in multi-layer PCBs. They consist of a drilled hole, a surrounding pad, and an isolated area on the power layers. The process involves electroplating the inner walls of the hole to connect copper layers from top to bottom. These vias can be directly connected to the upper or lower layers or left unconnected depending on the design. They serve both as electrical connections and for component mounting. Figure 1 shows a schematic of a standard via.
**2. Parasitic Capacitance of Vias**
Every via has a certain amount of parasitic capacitance relative to the ground plane. The formula for calculating this capacitance is approximately:
$$ C = 1.41 \cdot \varepsilon \cdot T \cdot D_1 / (D_2 - D_1) $$
Where:
- $ \varepsilon $ is the dielectric constant of the board material,
- $ T $ is the thickness of the PCB,
- $ D_1 $ is the diameter of the via pad,
- $ D_2 $ is the diameter of the via hole on the ground plane.
This parasitic capacitance can slow down signal transitions and reduce circuit speed. Therefore, minimizing it is crucial for high-speed applications.
**3. Parasitic Inductance of Vias**
Parasitic inductance is another important factor in high-speed designs. The inductance of a via can be approximated by:
$$ L = 5.08 \cdot h \left[ \ln\left( \frac{4h}{d} \right) + 1 \right] $$
Where:
- $ h $ is the length of the via,
- $ d $ is the diameter of the via’s central hole.
The inductance is more sensitive to the length of the via than its diameter. High inductance can degrade the performance of decoupling capacitors and affect the power integrity of the system.
**4. Non-Through-Hole Technology**
Non-through-hole technology includes blind and buried vias, which do not extend through the entire board. This approach reduces the number of layers required, improves electromagnetic compatibility, and allows for more compact designs. It also provides more space for routing, enhances shielding, and simplifies high-density layouts, especially for devices like BGAs.
Compared to traditional through-holes, non-through holes reduce manufacturing complexity and costs. With advancements in laser drilling and plasma etching, smaller vias are now feasible, leading to better performance and higher reliability.
**5. Via Selection in Standard PCBs**
In general PCB designs, the impact of via parasitics is less significant. For 1–4 layer boards, standard via sizes like 0.36mm/0.61mm/1.02mm (drill/pad/power isolation) are commonly used. Special signals such as power, ground, or clock lines may use larger vias (e.g., 0.41mm/0.81mm/1.32mm) for better performance.
**6. Via Design in High-Speed PCBs**
In high-speed PCB design, even small vias can have a major impact due to their parasitic effects. To minimize these effects, designers should consider the following:
- Choose appropriate via sizes based on layer count and density.
- Increase the power isolation area where possible.
- Minimize the number of vias to avoid unnecessary signal transitions.
- Use thinner PCBs to reduce parasitic parameters.
- Place power and ground vias close to their respective pins to reduce inductance.
- Add ground vias near signal vias to provide low-inductance return paths.
While smaller vias are generally better for high-speed performance, they come with increased manufacturing challenges and costs. Balancing performance, cost, and manufacturability is key in high-speed PCB design.
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