This article refers to the address: http://
Abstract: AC48105 is a dedicated voice processing chip produced by Israel's AudioCodes, which can be used to perform low-bit-rate voice compression coding and decompression and fax functions. The chip contains five independent multiplex channels for voice, fax and data transmission, and a 16-bit DSP core for multiple voice encoding formats. In this paper, the application mode and configuration method of the chip in low-speed speech coding equipment are introduced in detail.Key words: AC48105; DSP core; working mode; speech compression coding
AC48105 is a dedicated voice processing chip produced by AudioCodes. It has low bit rate voice compression coding, decompression and fax functions. It contains 5 independent channels for transmitting voice, fax and data. . The chip core is a 16-bit DSP, which is solidified with various encoding operation formats provided by the chip itself. This paper will mainly introduce the specific method of AC48105 in the low-speed speech coding device to realize the voice compression and decompression functions by configuring the DSP core.
1 main performance
Speech compression coding is relative to 64 kbps PCM (Pulse Code Modulation) conventional speech coding. In recent years, the research on low bit rate speech coding has made a big leap. At present, there are even speech coding algorithms with a rate of about 1 kbps. The dedicated voice processing chip AC48105 can provide a variety of low bit rate speech encoding formats and services, the specific content is as follows:
â— Based on G. 8kbps CS-ACELP speech coding of the 729 (A) protocol;
â— Based on G. 6.3/5.3 kbps MP-MLQ speech coding of the 723.1 protocol;
â— Based on G. 726/G. 16 to 40 kbps ADPCM and E-ADPCM speech coding of the 727 protocol;
◠Based on G. 64 kbps μ-law/A-law PCM speech coding of the 711 protocol;
â— NetCoder speech coding of 6.4, 7.2, 8.0, 8.8, 9.6 kbps;
â— Based on G. Silence suppression of the 729 (attached B) protocol, including voice activation detection (VAD) and comfort noise generator (CNG);
figure 1
   ◠Based on G. VAD and CNG silence suppression for the 723.1 (A) protocol.
The main features of the AC48105 are:
â— Automatic voice/fax/data switching is possible;
â— Damaged packets are automatically repaired;
â—G. 168/G. Adaptive echo suppression of 165;
â— Interface with E&M, AB, ABCD;
â— has a signal transmission (CAS) function in the channel;
â— It can detect and regenerate TIA 464B DTMF signal;
â— In-band signal transmission (IBS), including MF R1, R2, SS-4, SS-5, AC15 and call process;
â— With programmable audio signal transmission function;
â— Control input and output gain;
â— On-chip high-speed interface with PCM, can support T1, E1 and Multiple E1 formats;
â— has a parallel host processor interface;
â— Real-time full-duplex work.
2 chip working mode and command
The core of the AC48105 is a 16-bit DSP that cures multiple encoding operations. Data exchange between the DSP core and the external host can be achieved through eight multiplexed address/data buses. The AC48105 has the following four modes of operation:
(1) Reset and Kernel Down-load Mode;
(2) Program download mode? Program Download Mode?;
(3) Initialization mode? Initiation Mode?;
(4) Run Mode (Idle State and Active State).
The above four modes together constitute the complete operation flow of the chip. Figure 1 is a sequence diagram of its operational mode.
   ◠Reset and kernel download mode
On power-up, this mode is enabled and when the reset signal is activated (RESET pin is clamped low), its core code is downloaded to the AC48105.
â—Programming download mode
The start of the program download mode needs to meet two conditions at the same time. One is that the host sets the HPIC register in the AC48105 to make the HINT signal high; the second is that the kernel download is successful.
At the end of the programming download, the chip automatically enters the initialization mode.
â—Initialization mode and command
When in this mode, the commands issued by the host are valid for the initialization mode of each channel of the chip. The main initialization commands and command formats are listed in Table 1 and Table 2, respectively.
Table 1 main initialization commands
| Command name | Opcode Value (Opcode Value) | Signaling |
| PCM command | 00h | irrelevant |
| Run command | 01h | irrelevant |
| Debug command | 03h | irrelevant |
| MSIG command | 04h | irrelevant |
| Extended Signal command | 06h | Only when ES=1 |
| Call Progress command | 07h | Only when ES=1 |
| User-defined audio commands | 08h | Only when ES=1 |
Table 2 Initialization Command Format
| Frame Title | Bit Number | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Syns Header | 0 | ID (identification number) | AAh | |||||||||||||
| Command Header | Length | OPCode (opcode) | ||||||||||||||
| Parameter 1 (parameter 1) | ||||||||||||||||
| ...... | ||||||||||||||||
| Parameter n (parameter n) | ||||||||||||||||
| Checksum Footer (checksum footer) | 0 | Sequence Number | Checksum | |||||||||||||
Each command has a sync header AA h. In the command header, the opcode is used to indicate the type of command, and the length field is used to indicate the number of bytes in the command (hexadecimal).
When the host issues the Run command, the chip enters the run mode.
â— Operating mode (including idle state and active state)
Once the chip enters this mode, all channels are placed in an idle state, at which point the host begins to set operating parameters for each channel. When a channel is in an idle state, the time slot it occupies is generally not lost.
Unlike the initialization mode, the commands in the run mode are only valid for a single channel.
If there are multiple AC48105 chips in the system, the host must configure each chip in turn. Table 3 lists the command formats for the idle state.
Table 3 Idle State Command Format
| Frame Title | Bit Number | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Sync Header | 00h | AAh | ||||||||||||||
| Command Header | Length | OPCode (opcode) | ||||||||||||||
| Parameter 1 (parameter 1) | ||||||||||||||||
| ...... | ||||||||||||||||
| Parameter[(Length-4)/2](parameter (Length-4)/2]) | ||||||||||||||||
After entering the active state from the idle state, the data packet will be transmitted between the AC48105 and the host through the active channel in each frame gap. For voice transmission, the frame gap length is determined by the current speech coding mode and the number of blocks of the packet payload.
3 chip and host interface (HPI)
The HPI (Host Port Interface) is an 8-bit parallel interface that allows the host to access the internal memory of the voice chip through the HPI. Since the core of the voice chip is a 16-bit processor, in order to coordinate the data transfer between the host and the AC48105, HPI automatically converts the data from the on-chip memory from words to two bytes. The two bytes of data are compressed into a word form before the data is written to the on-chip memory. The on-chip memory that HPI can access is 2kB, and the address is 1000H~17FFH. At the same time, the host can also access these addresses through HPI. The allocation of related addresses is listed in Table 4.
Table 4 HPI address allocation
| Address range | Register/buffer | Register contents |
| 1000 | Kernel download buffer | - |
| 104B | Import status register | Full packet = 0, empty packet = 1, checksum error = 2 |
| 104C | Program download block buffer | - |
| 166D | Storage packet number buffer | The range is 0-15 |
| 166E | Host read packet status buffer | Full packet = 0, empty packet = 1 |
| 166F | Host write packet status buffer | Full packet = 0, empty packet = 1 |
| 1670-1737 | Host write buffer | |
| 1738-17FF | Host write buffer |
In fact, the HPI only needs to access the four registers of the on-chip memory, which are: control register, address register and data register, wherein the data register is divided into two types: address automatic accumulation and address not affected.
4 Application in digital program-controlled switches
4.1 System Introduction
The functions that low-speed speech coding and data exchange equipment can accomplish are mainly to realize 30-way local user calls based on digital exchange; 5 to 14 inter-office voice exchange, voice compression and multiplexing, and speed adjustable at 64k, 128k, 256k, and telephone Conference, full attendant functions, and implementation of computer monitoring. The equipment is modular in design and can be divided into the following modules according to functions: switching and control module, user circuit module, voice compression and multiplexing module, and regulated power supply and interface. The relationship between the various modules is shown in Figure 2.
4.2 How the voice compression module works and workflow
The module uses three AC48105 chips, each chip can be configured into five independent channels, corresponding to five time slots, so that the three chips can process a total of 15 time slot signals, corresponding to 15 relay user information. At the same time, each piece of AC48105 also carries a piece of SRAM, which is used to provide the required space for its internal DSP operation, but the host does not have additional control over the SRAM.
In this system, the host adopts Atmel's AT89C52 single-chip microcomputer, in which P0 port is used as the data/address low 8-bit multiplexing; P2 port is used as the upper 8 bits of the address, the design only uses A8, A9, A13, A14, A15; P1.0, P1.1, and P1.2 of the P1 port are respectively used as reset signals of the three-piece voice compression chip, and P1.3 is used as a read/write multiplexed signal of the compression chip. At the same time, the separate read and write signals of the compression chip are respectively connected to the read and write control ports of the single chip (ie, P3.6 and P3.7 of the P3 port). The MCU can access three voice chips through high-order address decoding. The specific operation is as follows: connect A15, A14 and A13 to 3~8 decoder in FPGA, strobe voice chip B when 000 is strobed voice chip A, 001, At 010, the voice chip C is strobed.
   The coding protocol used is G. 729. In this protocol, 10ms is a speech frame, and each frame contains 80 samples. These 80 samples are not ordinary speech signals, but some CELP mode parameters, including line spectrum pairs, adaptive codebook delay, and pitch delay parity. Sex, fixed codebook indicator, fixed codebook symbol, codebook gain (level 1), codebook gain (level 2), etc. After encoding and transmitting these parameters, they can be used at the decoder end. Restore the parameters of the excitation and synthesis filters. In this way, after power-on, the voice chip starts to load the two software program codes it needs: kernel code and program code. These two files occupy a total of 122k Bytes of space, and an optional Atmel is available. The AT2C010-128k×8 E2PROM memory is used for storage. The access to the E2PROM can be obtained by decoding the A15, A14, and A13 and reading signals from the MCU. It is worth noting that the addressing of the E2PROM by the MCU must be performed sequentially. The two softwares are placed in order from the first address of the E2PROM. When the two softwares are sequentially downloaded to a piece of voice chip, a hardware clear will be generated inside the FPGA. So that the address pointer of the E2PROM points again to the first address for the download of the next piece of voice chip. After the three AC48105s are properly loaded, the microcontroller begins to configure its operating state and then performs a compression/decompression operation. Since only 15 packets of data can be stored in each voice chip, that is, each channel has 3 packets of data, and each packet represents 10 ms of voice frames. Therefore, the MCU needs to poll three voice chips in turn in a sufficiently effective time period. Otherwise, There will be leaks and large data loss. Therefore, the data exchange between the MCU and the three voice chips requires a buffer. In this system, this buffer is completed by the dual-port RAM inside the FPGA. The clock for writing and reading data in the dual-port RAM can be different, which ensures that the data is not affected when writing and reading data.
When the activation command is run in the idle state, the voice chip enters an active state, at which time the voice chip begins to exchange data with the microcontroller. At G. Under the 729 protocol, each packet of data represents 10ms of voice data (called a voice frame), a total of 80Bytes. When the MCU writes the data to be compressed to the voice chip, it needs to add a 16Bytes command header to the frame header of each voice frame. In the middle is the voice data, and the suffix of 0~4Bytes is added at the end. Conversely, when the MCU extracts the decompressed data from the voice chip, the frame header of each speech frame also has a 16 Bytes status header generated by the DSP core of the voice chip, followed by the voice data of the state header, and the end is 0 to 4 Bytes. suffix.
GPS Personal Tracker Co., Ltd. , http://www.szgpstracker.com