Abstract: Using FIFO to synchronize data from different clock domains is a method often used in digital IC design. FUFO with correct design functions will encounter many problems and discuss the design ideas of two different asynchronous FIFOs. Both ideas can achieve PIFO with correct function.
From the hardware point of view, the FIFO studied in this article is a piece of data memory. It has two ports, one for writing data, that is, storing data in FIFO; the other for reading data, that is, taking data from FIFO. There are two pointers related to the FIFO operation, the write pointer points to the memory section to be written, and the read pointer points to the memory section to be read. The FIFO controller controls the movement of these two pointers through external read and write signals, and thus generates a FIFO empty signal or a full signal.
For an asynchronous FIFO, data is written into the FIFO by a control signal in a certain clock domain, and data is read out of the FIFO by a control signal in another clock domain. In other words, the change of the reading and writing pointer is generated by different clocks. Therefore, the judgment of FIFO empty or full is across the clock domain. How to correctly judge the full or empty state of the FIFO according to the asynchronous pointer signal is the focus of this study. In addition, some details in the design process will also be involved in the article.
1 Pointer and full empty signal generation
In order to better explain the problem, first discuss the process of synchronous FIFO pointer movement and the generation of full and empty signals. For the synchronous FIFO, both the read and write pointers point to the initial location of a memory. Each time a read and write operation is performed, the corresponding pointer is incremented once to point to the next memory location. When the pointer moves to the last position in memory, it jumps back to the original position again. In the case where the FIFO is not full or empty, this process will continue with the change of the read and write control signals. If the FIFO is empty, the next read action will result in an underflow and an invalid data will be read; similarly, for a full FIFO, writing will cause an overflow (overflow), A useful data is overwritten by the newly written data. Both of these cases are misoperations, so two signals, full and empty, need to be set. Setting the full signal means that the FIFO is in a full state, resetting the full signal means that the FIFO is not full, and there is room to write data; Set to indicate that the FIFO is in an empty state, resetting the empty signal indicates that the FIFO is not empty, and valid data can be read out. 
When the read pointer and the write pointer are equal, that is, point to the same memory location, the FIFO may be in a full or empty state. Different methods can be used to judge or distinguish whether the FIFO is in a full state or an empty state, that is, whether the write pointer catches up with the read pointer afterwards, or whether the read pointer catches up with the write pointer afterwards. The method used in this article is to set an additional status bit, the pointer consists of its address bit and status bit. The address bit increases with the corresponding operation, and the status bit is reversed when the pointer returns from the last position of the memory to the initial position. Therefore, when the address bit and the status bit of the read and write pointer all coincide, the read and write pointer has undergone the same number of cyclic movements, that is, the FIFO is in an empty state (Figure 1 (a)); if the address of the read and write pointer The bits are the same and the status bits are reversed. The write pointer loops once more than the read pointer, marking the FIFO is in a full state (Figure 1 (b)).
2 Synchronization of binary pointer and Gray code pointer
The binary pointer is composed of a single-bit status bit and several binary-coded address bits (for example, the change of the pointer composed of three-bit address and one-bit status bit: 0000 → 0001 → 0010 → 0011 → 0100 → 0101 → 0110 → 0111 → 1000 → 1001 → 1010 → 1011 → 1100 → 1101 → 1110 → 1111). If the binary pointers are directly synchronized in different clock domains, there may be problems. For example, when the read pointer changes from 0111 to 1000, all the bits of the pointer must change. If the write clock is sampled at the moment when the read pointer changes, the read pointer value obtained by the writer may be any of 0000 to 1111. One. Therefore, the binary pointer should not be directly synchronized, but the binary pointer can be synchronized by a pair of handshake signals.
For example, when the read pointer is stored in a register by the reader, the reader sends a ready signal. When the writer sees the ready signal, it reads the read pointer and issues a confirmation signal that it has received the data. When the reader sees the confirmation signal, it withdraws the ready signal, and then refreshes the register with the current read pointer value (Figure 2). Before receiving the confirmation signal, the content of the register storing the read pointer remains unchanged, ensuring the accuracy of the read pointer.
In order to be able to synchronize the pointers directly in different clock domains, the Gray coding method can be used for the pointers, that is, the pointer changes only one bit per movement, thus avoiding the problem that the pointer cannot be synchronized directly because multiple pointers change simultaneously. Figure 3 shows a three-bit address memory used for Gray coded FIFO. The n-bit address memory requires n + 1-bit Gray code. Use the highest bit (that is, the n-1 bit) as the status bit, from the n-2 to the 0th bit as the address from the n-2 bit to the 0th bit; for the status bit (that is, the n-1 bit) XOR with the n-2 bit to generate the n-2 bit of the address (that is, the highest bit of the address). It can be seen from the observation of Figure 3 that the pointer encoded by the four-bit Gray code and the pointer encoded by the three-bit binary plus status bits have the same function: the address generated by the pointer loops through 8 memory addresses, and the status bit is taken after each traversal anti. It is worth noting that when the pointer changes from 0100 to 1100, the corresponding address changes from 100 to 000, and the status bit and one bit address have changed at the same time, so the state generated by the gray code pointer of another clock domain cannot be synchronized. Bits and address bits, at this time should be directly completed by another clock domain synchronization pointer, and the corresponding status bit and address bit are generated by the synchronized pointer. 
3 Conservative full empty judgment
For the design of asynchronous FIFO, whether to use handshake or direct synchronization to obtain the pointer of the other party's clock domain, the judgment of the full and empty signal is always "conservative".
(1) The reset of the full empty signal (full signal reset indicates that the FIFO is not full, and the reset of the empty signal indicates that the FIFO is not empty) has a certain delay compared with the actual FIFO. For example, the null signal is generated by the reader comparing the read pointer with the write pointer obtained after synchronization or handshake. Because synchronization or handshake takes a certain amount of time, during this time, the writer may write new data to the FIFO, and the write pointer has changed. At this time, the FIFO is not empty, but the empty signal is still not reset at this moment. For the writer, the reset of the full signal will also encounter the same problem. However, under normal circumstances, as long as the FIFO does not overflow or overflow, the reset delay will not cause overflow or overflow, which is acceptable.
(2) The setting of the full-empty signal (full signal setting indicates that the FIFO is full, and the empty signal setting indicates that the FIFO is empty) and there is no delay compared with the actual situation of the FIFO. For example, also consider the case where the FIFO is empty, the reader uses the read pointer to compare with the write pointer after synchronization or handshake. Since the FIFO is empty, the write action does not occur, and the corresponding write pointer remains unchanged, so the reader gets The value of the write pointer at that time. This will set the null signal immediately. Similarly, when the FIFO is full, since the read pointer does not change, the writer gets the current read pointer value, and can immediately determine that the FIFO is full.
From the discussion of the above two points, it can be concluded that the FIFO full and empty judgment is conservative. The writer may stop writing data when the FIFO still has a certain space, but will not continue to write data when the FIFO is full; the reader may Stop reading data when the FIFO has some valid data, but will not continue to read data when the FIFO is empty. The conservative full-empty judgment can meet the functional requirements of the FIFO.
4 Comparison of binary pointer and Gray code pointer
Both binary pointers and Gray code pointers have their own advantages and disadvantages:
(1) Due to the synchronization through handshake, the pointer can have multiple bits changing at the same time, and the binary pointer can jump over any length every time it moves, which brings convenience to the realization of some functions of the FIFO (for example, the hardware directly controls the FIFO slave buffer A wrong packet is discarded in the data stream); and the Gray code pointer can generally only move in increments or decrements. 
(2) Binary pointers can be used for FIFOs of any size; Gray code pointers can only be used for FIFOs of size 2 power.
(3) Compared with direct synchronization, synchronization through handshake requires multiple clock cycles, so the full-empty judgment of binary pointers is more "conservative" than that of Gray code pointers; Said that the space lost due to conservative judgment can be ignored; but for a FIFO with a smaller capacity, this "conservative" may be unacceptable. For example, a FIFO composed of 8 registers, for a pointer coded by Gray code, in the worst case, when the FIFO is judged to be full by the writer, there are actually only five data stored in it (using a two-stage synchronizer may require three Cycle synchronization, and during all three cycles a read action occurs); and for the pointer with binary encoding, when the FIFO is judged to be full, there may be only three data or less in the FIFO (using a two-stage synchronizer, In the best case, a five-cycle handshake is required, and during these five cycles a read action occurs).
The designer should consider the above points when comparing the two methods.
Two different ways of designing the asynchronous FIFO introduced in this article can achieve a functioning asynchronous FIFO. A brief analysis of the advantages and disadvantages of the FIFO designed by these two methods has guiding significance for the design of the FIFO.
LED Wall Wash Light
Wall Wash Light Series Include 36x12w LED Wash light, 19x15w Led wash light; Both is hot selling in the lighting market.
36X12W RGBW 4 IN 1/5 IN 1/6 IN 1 /LED Wash Moving Head Light
Specification:
Pure bright in color effect, excellent color mixing, good heat cooling
36 pcs 12W RGBWA+UV 6in1 LED, 36 pcs 10W RGBWA 5in1 LED, 36 pcs 10W RGBW 4in1 LED
10-60 zoom angle, narrow beam effect to wide wash effect, functional in usage.
Small size, easy to carry and install, each unit weighs only 9kg
Linear smooth dimmer from 0-100%, 1-20 times strobe per second, flicker-free for TV and films.
Suitable for mobile productions, events, parties, stage installations, theater, musical concert, TV studios.
Our company have 13 years experience of LED Display and Stage Lights , our company mainly produce Indoor Rental LED Display, Outdoor Rental LED Display, Transparent LED Display,Indoor Fixed Indoor LED Display, Outdoor Fixed LED Display, Poster LED Display , Dance LED Display ... In additional, we also produce stage lights, such as beam lights Series, moving head lights Series, LED Par Light Series and son on...
Wall Wash Light Series,Disco Light,Led Washer Light,Moving Head
Guangzhou Chengwen Photoelectric Technology co.,ltd , https://www.cwleddisplay.com